A compression-based area-efficient recovery architecture for nonvolatile processors
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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Adiabatic switching techniques based on energy recovery principle are one of the innovative solutions at circuit and logic level to achieve reduction in power. Many researchers had taken adder as a benchmark circuit but advantage of adiabatic can be taken only for a large digital circuit. Barrel Shifter is an important block in the processor design and not much effort has been done to minimize it’s power dissipation. A barrel shifter needs nlog2n MUX for n-bit shifting and therefore designing a MUX for low power to use it as a repetitive block in the barrel shifter will considerably reduce the simulation time. This paper compares conventional CMOS based design with adiabatic All the circuits are designed using cell based design approach and 180nm device size in Cadence. The outcome of this research work will provide guidelines for designing barrel shifter using ultra low power MUX .