Understanding bloom filter intersection for lazy address-set disambiguation
Proceedings of the twenty-third annual ACM symposium on Parallelism in algorithms and architectures
Reconstructing hardware transactional memory for workload optimized systems
APPT'11 Proceedings of the 9th international conference on Advanced parallel processing technologies
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Transactional memory (TM) provides efficient, easy, deadlock-free parallel programming model for today's multicore-ubiquitous hardware platform. Implementation of TM needs to guarantee that the transaction is executed atomically and in isolation. Our paper proposes an efficient and unbounded hybrid-mode TM system with strong isolation guarantee, called HybridTCache. HybridTCache optimizes the common case by executing small transactions completely by hardware, and triggers operating system (OS) support with low overhead for the uncommon case when transaction size exceeds the hardware capacity. HybridTCache adds a new L1 cache, named TCache, to buffer transactional data for the active transaction executed by the processor. Compared with traditional log based approach, TCache provides fast bookkeeping which eliminates software logging overhead for the un-overflowed blocks, thus making both transaction commit and abort fast. A key design point of hardware TM is to support unbounded transactions. HybridTCache achieves this by introducing TCache overflow exceptions and resorting to OS to handle the overflowed blocks.