Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Proceedings of the 2012 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools
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Configurable processors are adopted by several latest embedded system projects to make use of application specific custom instructions for instruction level parallelism. Meanwhile, designers also use multiple processors for thread level parallelism. Configurable Heterogeneous Multi-Processor System-on-Chip (CH-MPSoC) has both parallelism advantages and seems to be a good solution for future embedded systems. Because CH-MPSoC has lots of architectural parameters, new design methodologies are required to help exploring this huge design space and finding a suitable solution for all user-defined constraints. We propose a new exploration flow using a budget based problem partitioning approach integrated with multiple abstraction levels. By using several abstraction levels, global budgets of speed, power and cost can be decomposed into detailed ones which are mapped onto each component. One special abstraction level called Transaction Accurate level is used in our flow to model both multi-processor architectures and configurable processors. At this level, hardware tasks and peripherals use transaction level modeling to achieve high simulation speed. Statistic information of configurable processors is abstracted and annotated to each software tasks. The execution results are used to adjust budgets and guide automatic extended instructions generation. With the Motion-JPEG case study, we illustrate detailed advantages of our CH-MPSoC exploration flow.