Design of Analog CMOS Integrated Circuits
Design of Analog CMOS Integrated Circuits
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This paper presents the design and implementation of three poweramplifiers (PAs) for 3.1 to 4.8GHz UWB communication system in0.18μm CMOS technology. The proposed PAs are biased with asingle 1V DC power supply. The first PA, a single-stage amplifierachieves a maximum power gain of +7.05dB at 3.25GHz, an input P1dBof -5.1dBm and output IP3 of +12dBm at 4GHz, while consuming 21mWof DC dissipation. The second PA is a two-stage amplifier and ithas +13.5dB of maximum gain at 3.2GHz, -2.5dBm of input P1dB and+16dBm of output IP3 at 4GHz, with a power consumption of 28.3mW.The final PA, a two-stage cascode amplifier has a maximum gain of14.7dB, input P1dB of -9.1dBm and output IP3 of +13dBm at 4GHz,consuming 20.2mW from the 1V supply. Measurement results obtainedare used to create a nonlinear power-dependent S-parameter (P2D)file that serves as a behavioural model used to determine theoptimum input and output matching required for each PA. Finally,advanced simulations with the UWB modulated test signals in theenvelope domain, including simulations and analysis of outputspectrum and channel power using the created P2D PA models are alsoillustrated.