Materials and processing for 0.25 &mgr;m multilevel interconnect
AMI '96 Proceedings of the symposium J of the 1996 E-MRS Spring meeting conference on Advanced materials for interconnections
Copper CMP evaluation: planarization issues
Microelectronic Engineering
Dependency of dishing on polish time and slurry chemistry in Cu CMP
Proceedings of the third Europeon workshop on Materials for advanced metallization
Inverse analysis of material removal data using a multiscale CMP model
Microelectronic Engineering
Microelectronic Engineering - Proceedings of the European workshop on materials for advanced metallization 2004
Maintenance Optimization Of Equipment By Linear Programming
Probability in the Engineering and Informational Sciences
Effect of frictional force vector on delamination in Cu/low-k integration
Microelectronic Engineering
Effect of organic acids on copper chemical mechanical polishing
Microelectronic Engineering
Chemical mechanical planarization operation via dynamic programming
Microelectronic Engineering
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Electro-chemical mechanical planarization (ECMP) process dissolves copper ions electrochemically by applying an anodic potential on the copper surface in an aqueous electrolyte, and then removes a copper (Cu) complex layer by the mechanical abrasion of a polishing pad or abrasives in the electrolyte. The ECMP process is a low pressure polishing method for metals such as copper, aluminium (Al) and tungsten (W) on dielectric materials such as silicon dioxide, low-k (LK) and ultra low-k (ULK) dielectrics, comparing to the amount of defects by the traditional Cu chemical mechanical planarization (CMP). The polishing pad used in the ECMP process is a conventional closed cell type pad (IC 1400K-groove pad) with holes. It supplies the aqueous electrolyte to the copper surface and removes the copper complex layer. The material removal rate (MRR) and MRR profile were simulated and tested according to the changes of the wafer overhang distance (WOD) from the platen and the electric contact area (ECA). In order to derive the design rule of the system, the experimental results are compared with the simulation results. After the ECMP process, it was verified that the within wafer non-uniformity (WIWNU) was lower than 2% using the relatively uniform ECA pad (C-type) under the smallest WOD condition. The experimental results well matched the simulated results.