Faulty-tolerant algorithm for mapping a complete binary tree in an IEH

Authors:
Shih-Jung Wu;Jen-Chih Lin;Huan-Chao Keh
Affiliations:
Department of Computer Science and Information Engineering, Nanya Institute of Technology, Jhongli City, Taoyuan County, Taiwan, R.O.C.;Department of Digital Content Design, National Taipei University of Education, Taipei City, Taiwan, R.O.C.;Department of Computer Science and Information Engineering, Tamkang University, Tamsui, Taipei, Taiwan, R.O.C.
Venue:
WSEAS Transactions on Computers
Year:
2008

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Abstract

Different parallel architectures may require different algorithms to make the existent algorithms on one architecture be easily transformed to or implemented on another architecture. This paper proposes a novel algorithm for embedding complete binary trees in a faulty Incrementally Extensible Hypercube (IEH). Furthermore, to obtain the replaceable node of the faulty node, 2-expansion is permitted such that up to (n+1) faults can be tolerated with dilation 3, congestion 1 and load 1. The presented embedding methods are optimized mainly for balancing the processor loads, while minimizing dilation and congestion as far as possible. According to the result, we can map the parallel algorithms developed by the structure of complete binary tree in an IEH. These methods of reconfiguring enable extremely high-speed parallel computation.