Load-balance and fault-tolerance for embedding a complete binary tree in an IEH with N-expansion

  • Authors:
  • Jen-Chih Lin

  • Affiliations:
  • Department of Digital Content Design, National Taipei University of Education, Taipei City, Taiwan, R.O.C.

  • Venue:
  • WSEAS Transactions on Computers
  • Year:
  • 2008

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Abstract

Embedding is of great importance in the applications of parallel computing. Every parallel application has its intrinsic communication pattern. The communication pattern graph is embedded in the topology of multiprocessor structures so that the corresponding application can be executed. This paper presents strategies for reconfiguring a complete binary tree in a faulty Incrementally Extensible Hypercube (IEH) with N-expansion. This embedding algorithm show a complete binary tree can be embedded in a faulty IEH with dilation 4, load 1, and congestion 1 such that O(n2-h2) faults can be tolerated, where n is the dimension of IEH and (h-1) is the height of a complete binary tree. Furthermore, the presented embedding methods are optimized mainly for balancing the processor loads, while minimizing dilation and congestion as far as possible. According to the result, we can embed the parallel algorithms developed by the structure of complete binary tree in an IEH. This methodology of embedding enables extremely high-speed parallel computation.