System architecture directions for networked sensors
ASPLOS IX Proceedings of the ninth international conference on Architectural support for programming languages and operating systems
Computer Architecture: A Quantitative Approach
Computer Architecture: A Quantitative Approach
An ultra low-power processor for sensor networks
ASPLOS XI Proceedings of the 11th international conference on Architectural support for programming languages and operating systems
Proceedings of the 2005 international conference on Compilers, architectures and synthesis for embedded systems
WISENEP: A Network Processor for Wireless Sensor Networks
ISCC '06 Proceedings of the 11th IEEE Symposium on Computers and Communications
Architectural optimization for performance- and energy-constrained sensor processors
Architectural optimization for performance- and energy-constrained sensor processors
Protothreads: simplifying event-driven programming of memory-constrained embedded systems
Proceedings of the 4th international conference on Embedded networked sensor systems
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Sensor platforms designed with mobility in mind, such as body networks, have inherent scalability problems arising from the conflicting demand for high processing capabilities (to collect, compress, and filter data) and the need for low-power, resource-constrained hardware. This paper presents a CPU design which seeks to optimize processing for a sensor network by improving performance in a power-efficient and scalable manner. We demonstrate the crucial design decisions and trade-offs required in developing such a processing platform and demonstrate that a minimalist design saves power without adverse impact on performance. In addition, we address the problem of scalability in a multithreaded environment through the development of a novel scheduling algorithm implemented directly in hardware.