Motion Field and Optical Flow: Qualitative Properties
IEEE Transactions on Pattern Analysis and Machine Intelligence
Performance of optical flow techniques
International Journal of Computer Vision
Electronic digital image stabilization: design and evaluation, with applications
Electronic digital image stabilization: design and evaluation, with applications
Shooting a smooth video with a shaky camera
Machine Vision and Applications
The evaluation of normalized cross correlations for defect detection
Pattern Recognition Letters
SIMD, SMP and MIMD-DM Parallel Approaches for Real-Time 2D Image Stabilization
CAMP '05 Proceedings of the Seventh International Workshop on Computer Architecture for Machine Perception
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Highly regular multi-processor architecture are suitable for inherently highly parallelizable applications such as most of the image processing domain. System on a programmable chip (SoPC) allows hardware designers to tailor every aspects of the architecture in order to match the specific application needs. These platforms are now large enough to embed an increasing number of core, allowing implementation of a multi-processor architecture with an embedded communication network. In this paper we present the parallelization and the embedding of a real time image stabilization algorithm on SoPC platform. Our overall hardware implementation method is based upon meeting algorithm processing power requirement and communication needs with refinement of a generic parallel architecture model. Actual implementation is done by the choice and parameterization of readily available reconfigurable hardware modules and customizable commercially available IPs. We present both software and hardware implementation with performance results on a Xilinx SoPC target.