A real-time wavelet-domain video denoising implementation in FPGA
EURASIP Journal on Embedded Systems
Bivariate shrinkage functions for wavelet-based denoising exploiting interscale dependency
IEEE Transactions on Signal Processing
De-noising by soft-thresholding
IEEE Transactions on Information Theory
Perception adaptive temporal TV-noise reduction using contour preserving prefilter techniques
IEEE Transactions on Consumer Electronics
IC for motion-compensated de-interlacing, noise reduction, and picture-rate conversion
IEEE Transactions on Consumer Electronics
Adaptive wavelet thresholding for image denoising and compression
IEEE Transactions on Image Processing
A joint inter- and intrascale statistical model for Bayesian wavelet based image denoising
IEEE Transactions on Image Processing
Image quality assessment: from error visibility to structural similarity
IEEE Transactions on Image Processing
Feature-based wavelet shrinkage algorithm for image denoising
IEEE Transactions on Image Processing
Wavelet-Domain Video Denoising Based on Reliability Measures
IEEE Transactions on Circuits and Systems for Video Technology
| Hi-index | 0.00 |
In this paper we present a wavelet-based video enhancement algorithm designed for highly optimized dedicated ICs. The proposed algorithm is implemented on FPGA platform with target being real-time video processing. The main application of the proposed scheme is a high definition (HD) TV, where we consider visibly annoying video coding artifacts and noise (assumed as white Gaussian). In the proposed denoising scheme each video frame is processed independently, i.e., only spatial filtering is performed. Specifically, two-dimensional (2D) non-decimated wavelet transform is applied to the frame, after which the proposed activity-adaptive shrinkage operation on the wavelet coefficients is done. Finally, the denoised image is reconstructed by inverse wavelet transform. The main contribution of the paper is the proposed (i) hardware-friendly scheme for the wavelet decomposition - reconstruction framework with full parallelism and reduced memory resources required and (ii) efficient and low computationally expensive activity-adaptive shrinkage algorithm for denoising. The designed framework is verified in SystemC and on FPGA platform with WXGA Panel. The annoying artifacts and noise are shown to be efficiently removed with small or no visible reduction in spatial resolution.