High speed ferrite 2 1/2 D memory
AFIPS '65 (Fall, part I) Proceedings of the November 30--December 1, 1965, fall joint computer conference, part I
AFIPS '68 (Fall, part II) Proceedings of the December 9-11, 1968, fall joint computer conference, part II
Real-time fault detection for small computers
AFIPS '72 (Spring) Proceedings of the May 16-18, 1972, spring joint computer conference
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The obvious cost advantage of a 2-wire 2-1/2D core mat over a 3-wire mat has, in the past, been offset by the increased complexity of the access and detection circuitry required for a 2-wire array. This paper will concentrate on 2-wire bit accessing schemes and describe one which appears to be cheaper and less noisy than the conventional bit access which uses a complete matrix per bit. It will then discuss the readout noise problems. To predict the amplitude of noise a multistate core model similar to J. Reese Brown's will be developed. The paper will then show how the individual core characteristics can be extrapolated to predict overall optimum memory performance.