A 105-bit high-speed ferrite memory system: design and operation
AFIPS '64 (Fall, part I) Proceedings of the October 27-29, 1964, fall joint computer conference, part I
A 500-nanosecond main computer memory utilizing plated-wire elements
AFIPS '66 (Fall) Proceedings of the November 7-10, 1966, fall joint computer conference
Bit access problems in 2-1/2D 2-wire memories
AFIPS '67 (Fall) Proceedings of the November 14-16, 1967, fall joint computer conference
AFIPS '68 (Spring) Proceedings of the April 30--May 2, 1968, spring joint computer conference
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Main core storage in digital computers has been getting both larger and faster with each generation. In view of this a design was undertaken which would be inherently faster, and inherently less expensive in the large sizes. Other significant inputs to the design approach chosen was that electronics, that is semiconductors, were becoming less expensive; also, to operate at the higher speeds smaller cores must be used. Since it is progressively more difficult to put additional wires through these smaller cores, system approaches using fewer wires through the core were studied.