Modeling and evaluation of ring-based interconnects for Network-on-Chip
Journal of Systems Architecture: the EUROMICRO Journal
Real-time address trace compression for emulated and real system-on-chip processor core debugging
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
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Editor's note:This article advocates a systematic approach to improve NoC design quality by guiding architectural choices according to the difficulty of verification and test. The authors propose early quality metrics for added test, monitoring, and debug hardware.—Yatin Hoskote, Intel