Performance analysis of direct digital synthesizer architecture with amplitude sequencing

  • Authors:
  • I. Jivet;B. Dragoi

  • Affiliations:
  • Electronics and Telecommunications Department, University 'Politechnica' Timisoara, Timisoara, Romania;Electronics and Telecommunications Department, University 'Politechnica' Timisoara, Timisoara, Romania

  • Venue:
  • WSEAS Transactions on Circuits and Systems
  • Year:
  • 2008

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Abstract

The paper presents an analysis of a novel DDS architecture based on direct amplitude algorithmic generation in its capacity to generate pure and high frequency signals. The algorithm implementation requires very few resources and is linear in digital precision length. In its simplest form includes one compare, two additions and several increments per iteration step. A solution to compensate the known major drawback of the algorithm, sample phase non uniformity in time, is presented. The versatility of direct digital synthesizers in frequency switching and phase modulation applications is shown to be preserved in the new architecture. The paper also presents an analysis of the potential of the proposed architecture performance as reflected in the low harmonic spectrum of the quadrature output signals. A FPGA implementation of the architecture was synthesized and simulated using a VHDL description to validate the solution as proposed. Synthesis reports are compared with other FPGA direct frequency synthesizer implementations as reported in recent literature.