High-PSR-bandwidth capacitor-free LDO regulator with 50µA minimized load current requirement for achieving high efficiency at light loads

  • Authors:

  • Huan-Chien Yang;Ming-Hsin Huang;Ke-Horng Chen

  • Affiliations:

  • Electrical and Control Engineering National Chiao Tung University, Hsinchu, Taiwan;Electrical and Control Engineering National Chiao Tung University, Hsinchu, Taiwan;Electrical and Control Engineering National Chiao Tung University, Hsinchu, Taiwan

  • Venue:
  • WSEAS Transactions on Circuits and Systems
  • Year:
  • 2008

Quantified Score

Hi-index 0.00

Visualization

Abstract

A capacitor-free LDO regulator with the minimized-Q (MQ) and adaptive zero compensation (AZC) techniques is proposed in this paper. With the MQ technique, light load efficiency is greatly improved since only 50µA minimized load current is required. Furthermore, due to noise cancellation from power supply, the LDO regulator with the MQ technique has higher PSR bandwidth with compatible compensation capacitors compared to the Q-reduction technique [1]. Besides, fast transient response time is also achieved because phase margin equals to 60 degree is always maintained by the MQ and AZC techniques. The capacitor-free LDO regulator with the MQ and AZC techniques was fabricated in TSMC 0.35µm 2P4M CMOS process with small compensation capacitors 5pF and 1.5pF. Experimental results demonstrate that the minimum load can be reduced to about 50µA and transient response time can be reduced by the MQ and AZC techniques to be smaller than 4µs. The measured load and line regulation are 20µV/mA and 3.3mV/V respectively.