Analysis and Design of Analog Integrated Circuits
Analysis and Design of Analog Integrated Circuits
WSEAS Transactions on Circuits and Systems
Analog IC Design with Low-Dropout Regulators (LDOs)
Analog IC Design with Low-Dropout Regulators (LDOs)
Reverse nested miller compensation using current buffers in a three-stage LDO
IEEE Transactions on Circuits and Systems II: Express Briefs
A Hybrid Scheme for On-Chip Voltage Regulation in System-On-a-Chip (SOC)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A fully on-chip 1-μW capacitor-free low-dropout regulator with adaptive output stage
Analog Integrated Circuits and Signal Processing
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This paper presents a novel frequency compensation technique for a low-dropout (LDO) voltage regulator. Enhanced active feedback frequency compensation is employed to improve the frequency response. The proposed LDO is capable of providing high stability for current loads up to 150 mA with or without loading capacitors. The proposed LDO voltage regulator provides a loop bandwidth of 7.8 MHz under light loads and 6.5 MHz under heavy loads. The maximum undershoot and overshoot are 59 and 90 mV, respectively, for changes in load current within a 200-ns edge time, while the compensation capacitors only require a total value of 7 pF. This enables easy integration of the compensation capacitors within the LDO chip. The proposed LDO regulator was designed using TSMC 0.35-μm CMOS technology. With an active area of 0.14 mm2 (including feedback resistors), the quiescent current is only 40 μA. The input voltage ranges from 1.73 to 5 V for a loading current of 150 mA and an output voltage of 1.5 V. The main advantage of this approach is the stability of the LDO circuit when external load capacitors are connected, or even without load capacitors.