A fully on-chip 1-μW capacitor-free low-dropout regulator with adaptive output stage

Authors:
Xi Qu;Ze-Kun Zhou;Bo Zhang
Affiliations:
State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Chengdu, China;State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Chengdu, China;State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Chengdu, China
Venue:
Analog Integrated Circuits and Signal Processing
Year:
2014

Citing 7
Cited 0

A 3-A CMOS low-dropout regulator with adaptive Miller compensation

Analog Integrated Circuits and Signal Processing
A capacitor-less CMOS active feedback low-dropout regulator with slew-rate enhancement for portable on-chip application

IEEE Transactions on Circuits and Systems II: Express Briefs
Reverse nested miller compensation using current buffers in a three-stage LDO

IEEE Transactions on Circuits and Systems II: Express Briefs
A linear voltage regulator for an implantable device monitoring system

Analog Integrated Circuits and Signal Processing
A fully on-chip area-efficient CMOS low-dropout regulator with fast load regulation

Analog Integrated Circuits and Signal Processing
Current buffer compensation topologies for LDOs with improved transient performance

Analog Integrated Circuits and Signal Processing
Enhanced active feedback technique with dynamic compensation for low-dropout voltage regulator

Analog Integrated Circuits and Signal Processing

Quantified Score

Hi-index	0.00

Visualization

Abstract

A fully on-chip 1-μW fast-transient response capacitor-free low-dropout regulator (LDO) using adaptive output stage (AOS) is presented in this paper in standard 0.13-μm CMOS process. The AOS circuit is proposed to deliver extra four times of output current of the operational amplifier at medium to heavy load to extend the bandwidth of the LDO and enhance the slew rate at the gate of the power transistor. And the AOS circuit is shut off at light load to reduce the quiescent current and maintain the stability without requiring area-consuming on-chip capacitor. Meanwhile, the proposed AOS circuit introduces VOUT offset at medium to heavy load to counteract the VOUT drop, which is caused by ILOAD increase. Hence, transient performances of LDO and VOUT drop between light load and full load are improved significantly with 1.1-μA quiescent current at light load. From the post simulation results, the LDO regulates the output voltage at 0.7 V from a 0.9-V supply voltage with a 100-mA maximum load current. The undershoot, the overshoot and the recovery time of the proposed LDO with ILOAD switching from 50 μA to 100 mA in 1 μs are about 130 mV, 130 mV and 1.5 μs, respectively. And the VOUT drop between light load and full load reduces to 0.16 mV.