Characteristics of Prototype CMOS Quaternary Logic Encoder-Decoder Circuits

Authors:
J L Mangin;K W Current
Affiliations:
-;-
Venue:
IEEE Transactions on Computers
Year:
1986

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Abstract

The use of quaternary logic input and output signals for delivering information on and off chip could reduce the number of required package pins or increase the amount of information conveyed on a fixed number of package pins. In this correspondence, we discuss the performance of prototype CMOS binary-to-quaternary encoder and quaternary-to-binary decoder test circuits that have been realized on a gate array IC chip.