Reducing cache power with low-cost, multi-bit error-correcting codes
Proceedings of the 37th annual international symposium on Computer architecture
Understanding the Energy Consumption of Dynamic Random Access Memories
MICRO '43 Proceedings of the 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture
Power management of hybrid DRAM/PRAM-based main memory
Proceedings of the 48th Design Automation Conference
RAIDR: Retention-Aware Intelligent DRAM Refresh
Proceedings of the 39th Annual International Symposium on Computer Architecture
Combining RAM technologies for hard-error recovery in L1 data caches working at very-low power modes
Proceedings of the Conference on Design, Automation and Test in Europe
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Caches use data very differently than main memory does, so DRAM caches can have dramatically different refresh requirements. M aking canonical assumptions about retention times in DRAM can be drastic overkill within the cache context. U sing standard refresh rates may be unnecessary, and can be a significant waste of cache utilization and power. I n this article, we view " retention time" in a new way by using statistical populations more appropriate for caches, and we suggest uses of a cache' s inherent error- control mechanisms to reduce refresh rates by several orders of magnitude.