High Performance Hardware Architecture of Linear Filters for Intelligent Video Processing

Authors:
Tse-Wei Chen;Shao-Yi Chien
Affiliations:
Media IC and System Lab Graduate Institute of Electronics Engineering and Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan 106;Media IC and System Lab Graduate Institute of Electronics Engineering and Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan 106
Venue:
PCM '08 Proceedings of the 9th Pacific Rim Conference on Multimedia: Advances in Multimedia Information Processing
Year:
2008

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Abstract

Image filtering is an essential process in the field of image processing, and linear image filters with large kernels are especially significant for computer vision or intelligent video processing. In this paper, a high performance hardware architecture of linear image filters, which is designed for embedded system in mobile devices, is proposed and analyzed. This linear filter hardware is capable of dealing with a 15 by 15 kernel by using massively parallel processing elements, and it offers a set of configurable parameters, which generalizes the functionality to handle different kinds of linear filters in most applications.