Performance Characterization of Itanium® 2-Based Montecito Processor

Authors:
Darshan Desai;Gerolf F. Hoflehner;Arun Kejariwal;Daniel M. Lavery;Alexandru Nicolau;Alexander V. Veidenbaum;Cameron Mcnairy
Affiliations:
Intel Compiler Lab, Intel Corporation, Santa Clara, USA CA 95050;Intel Compiler Lab, Intel Corporation, Santa Clara, USA CA 95050;Center for Embedded Computer Systems, University of California, Irvine, Irvine, USA CA 92697;Intel Compiler Lab, Intel Corporation, Santa Clara, USA CA 95050;Center for Embedded Computer Systems, University of California, Irvine, Irvine, USA CA 92697;Center for Embedded Computer Systems, University of California, Irvine, Irvine, USA CA 92697;Intel Compiler Lab, Intel Corporation, Santa Clara, USA CA 95050
Venue:
Proceedings of the 2009 SPEC Benchmark Workshop on Computer Performance Evaluation and Benchmarking
Year:
2009

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Abstract

This paper presents the performance characteristics of the Intel®Itanium®2-based Montecito processor and compares its performance to the previous generation Madison processor. Measurements on both are done using the industry-standard SPEC CPU2006 benchmarks. The benchmarks were compiled using the Intel Fortran/C++ optimizing compiler and run using the reference data sets. We analyze a large set of processor parameters such as cache misses, TLB misses, branch prediction, bus transactions, resource and data stalls and instruction frequencies. Montecito achieves 1.14× and 1.16× higher (geometric mean) IPC on integer and floating-point applications. We believe that the results and analysis presented in this paper can potentially guide future IA-64 compiler and architectural research.