Page placement algorithms for large real-indexed caches
ACM Transactions on Computer Systems (TOCS)
Automatic measurement of memory hierarchy parameters
SIGMETRICS '05 Proceedings of the 2005 ACM SIGMETRICS international conference on Measurement and modeling of computer systems
Automatic measurement of instruction cache capacity
LCPC'05 Proceedings of the 18th international conference on Languages and Compilers for Parallel Computing
A refactoring method for cache-efficient swarm intelligence algorithms
Information Sciences: an International Journal
Can linear approximation improve performance prediction ?
EPEW'11 Proceedings of the 8th European conference on Computer Performance Engineering
Computer memory: why we should care what is under the hood
MEMICS'11 Proceedings of the 7th international conference on Mathematical and Engineering Methods in Computer Science
On the accuracy of cache sharing models
ICPE '12 Proceedings of the 3rd ACM/SPEC International Conference on Performance Engineering
Large-reach memory management unit caches
Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture
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The excellent performance of the contemporary x86 processors is partially due to the complexity of their memory architecture, which therefore plays a role in performance engineering efforts. Unfortunately, the detailed parameters of the memory architecture are often not easily available, which makes it difficult to design experiments and evaluate results when the memory architecture is involved. To remedy this lack of information, we present experiments that investigate detailed parameters of the memory architecture, focusing on such information that is typically not available elsewhere.