A Theory of Communicating Sequential Processes
Journal of the ACM (JACM)
Communicating sequential processes
Communicating sequential processes
Selected papers of the 3rd workshop on Concurrency and compositionality
ACM Transactions on Programming Languages and Systems (TOPLAS)
Computer-aided verification of coordinating processes: the automata-theoretic approach
Computer-aided verification of coordinating processes: the automata-theoretic approach
Action versus State based Logics for Transition Systems
Proceedings of the LITP Spring School on Theoretical Computer Science: Semantics of Systems of Concurrent Processes
Refusal Simulation and Interactive Games
AMAST '02 Proceedings of the 9th International Conference on Algebraic Methodology and Software Technology
TACAS '00 Proceedings of the 6th International Conference on Tools and Algorithms for Construction and Analysis of Systems: Held as Part of the European Joint Conferences on the Theory and Practice of Software, ETAPS 2000
Liveness and Fairness in Process-Algebraic Verification
CONCUR '01 Proceedings of the 12th International Conference on Concurrency Theory
Nets, Terms and Formulas (Cambridge Tracts in Theoretical Computer Science)
Nets, Terms and Formulas (Cambridge Tracts in Theoretical Computer Science)
Conjunction on processes: Full abstraction via ready-tree semantics
Theoretical Computer Science
Residual for Component Specifications
Electronic Notes in Theoretical Computer Science (ENTCS)
FSEN'07 Proceedings of the 2007 international conference on Fundamentals of software engineering
Ready simulation for concurrency: it's logical!
ICALP'07 Proceedings of the 34th international conference on Automata, Languages and Programming
Defining distances for all process semantics
FMOODS'12/FORTE'12 Proceedings of the 14th joint IFIP WG 6.1 international conference and Proceedings of the 32nd IFIP WG 6.1 international conference on Formal Techniques for Distributed Systems
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Previous work has introduced the setting of Logic LTS, together with a variant of ready simulation as fully-abstract refinement preorder, which allows one to compose operational specifications using a CSP-style parallel operator as well as the propositional connectives conjunction and disjunction. In this paper, we show how a temporal logic for specifying safety properties may be embedded into Logic LTS so that (a) the temporal operators are compositional for ready simulation and (b) ready simulation, when restricted to pairs of processes and formulas, coincides with the logic's satisfaction relation. The utility of this setting as a semantic foundation for mixed operational and temporal-logic specification languages is demonstrated via a simple example.