Communicating sequential processes
Communicating sequential processes
Algorithms in C++
The RAISE specification language
The RAISE specification language
A classical mind
The Theory and Practice of Concurrency
The Theory and Practice of Concurrency
How to Make FDR Spin LTL Model Checking of CSP by Refinement
FME '01 Proceedings of the International Symposium of Formal Methods Europe on Formal Methods for Increasing Software Productivity
Fast LTL to Büchi Automata Translation
CAV '01 Proceedings of the 13th International Conference on Computer Aided Verification
Specification translation of state machines from equational theories into rewrite theories
ICFEM'10 Proceedings of the 12th international conference on Formal engineering methods and software engineering
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The Raise Specification Language (RSL) is a modeling language which supports various specification styles. To apply model checking to RSL concurrent descriptions, we translate RSL specifications into the input language CSPM of FDR. FDR is the model checker for the process algebra CSP. First, we define a syntactic and semantic translation from the concurrent applicative subset of RSL to CSPM, and show that this translation is a strong bisimulation which preserves properties such as traces and deadlock. Consequently, results obtained by refinement checks in FDR are sound for the original RSL descriptions. Second, RSL uses Linear Temporal Logic (LTL) to specify desired properties, but FDR does not support LTL. LTL formulas may be translated to CSP test processes in order to check them with FDR. We build a tool which automates the translation of RSL specifications into CSPM and translates LTL formulas to CSP processes, enabling the model checking of LTL formulas over RSL descriptions with FDR.