A 1.41---1.72 GHz sigma-delta fractional-N frequency synthesizer with a PVT insensitive VCO and a new prescaler

  • Authors:

  • Bo Zhao;Xiaojian Mao;Huazhong Yang;Hui Wang

  • Affiliations:

  • Department of Electronics Engineering, Tsinghua University, Beijing, China;Department of Electronics Engineering, Tsinghua University, Beijing, China;Department of Electronics Engineering, Tsinghua University, Beijing, China;Department of Electronics Engineering, Tsinghua University, Beijing, China

  • Venue:
  • Analog Integrated Circuits and Signal Processing
  • Year:
  • 2009

Quantified Score

Hi-index 0.00

Visualization

Abstract

A 1.41---1.72 GHz fractional-N phase-locked loop (PLL) frequency synthesizer with a PVT insensitive voltage-controlled oscillator (VCO) is presented. In this PLL, a VCO with process, voltage, and temperature (PVT) insensitive bias circuit, and a divided-by-7/8 prescaler with improved multi-phase frequency divider are adopted. A novel multi-stage noise shaping (MASH) sigma-delta modulator (SDM) is adopted here. A new combination of low-current-mismatch charge pump (CP) and a phase/frequency detector (PFD) is proposed in this paper. Using Hejian Technology CMOS 0.18 μm analog and digital mixed-mode process, a fractional-N PLL prototype circuit is designed, the VCO in the prototype circuit can operate at a central frequency of 1.55 GHz, and its phase noise is 驴121 dBc/Hz at 1.0 MHz, the variety of phase noise is depressed by about 1.4 dB with the help of PVT insensitive bias. Under a 1.8-V supply voltage, the phase noise of the PLL is 驴113 dBc/Hz at 1.0 MHz.