CMOS wireless transceiver design
CMOS wireless transceiver design
RF System Design of Transceivers for Wireless Communications
RF System Design of Transceivers for Wireless Communications
Analog Integrated Circuits and Signal Processing
Design of Analog CMOS Integrated Circuits
Design of Analog CMOS Integrated Circuits
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A fully integrated Phase-Locked Loop (PLL) based transmitter and I/Q Local Oscillating (LO) signal generator used for half-duplex Wireless Sensor Networks (WSN) transceivers is proposed. Instead of one 430---435 MHz PLL for frequency synthesizing, a 1.72---1.74 GHz PLL is designed together with a 1/4 frequency divider. Then the chip area of the inductors in the Voltage-Controlled Oscillator (VCO) is decreased to about 1/16, and I/Q dual-path LO signals can be obtained without additional power consumption. A Gray-code controlled prescaler is proposed to avoid the glitches and uncertain states, and then the frequency dividing accuracy is improved by 17%. A Gauss Frequency Shift Keying (GFSK) transmitter with a pipeline modulator is proposed, the 1st and 2nd Adjacent Channel Power Ratio (ACPR) are 驴19.9 and 驴20.7 dBc, respectively. A mathematical spur model of 1/4 frequency dividers is built here, and then a low-spur 1/4 frequency divider composed of our proposed improved Current Mode Logic (CML) latches is designed. The testing results show that the reference spurs are 驴61.2 dBc@20 MHz and 驴57.7 dBc@40 MHz at the output of the PLL, and 驴70.5 dBc@20 MHz and 驴66.6 dBc@40 MHz at the output of our 1/4 divider. With 2.6-mW power consumption, our proposed 1/4 frequency divider has a phase-noise contribution of only 0.5 dBc/Hz@500 kHz and 0.2 dBc/Hz@1 MHz.