Design & analysis of fault tolerant digital systems
Design & analysis of fault tolerant digital systems
The existence of refinement mappings
Theoretical Computer Science
Theoretical Computer Science
Model checking and abstraction
ACM Transactions on Programming Languages and Systems (TOPLAS)
Property preserving abstractions for the verification of concurrent systems
Formal Methods in System Design - Special issue on computer-aided verification (based on CAV'92 workshop)
Abstract interpretation of reactive systems
ACM Transactions on Programming Languages and Systems (TOPLAS)
Specification and verification of fault-tolerance, timing, and scheduling
ACM Transactions on Programming Languages and Systems (TOPLAS)
Verification of a Leader Election Protocol: Formal Methods Applied to IEEE 1394
Formal Methods in System Design
Validating Requirements for Fault Tolerant Systems using Model Checking
ICRE '98 Proceedings of the 3rd International Conference on Requirements Engineering: Putting Requirements Engineering to Practice
Scaling up Uppaal Automatic Verification of Real-Time Systems Using Compositionality and Abstraction
FTRTFT '00 Proceedings of the 6th International Symposium on Formal Techniques in Real-Time and Fault-Tolerant Systems
On Abstraction in Software Verification
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
ARTS '99 Proceedings of the 5th International AMAST Workshop on Formal Methods for Real-Time and Probabilistic Systems
Verification of fault tolerance and real time
FTCS '96 Proceedings of the The Twenty-Sixth Annual International Symposium on Fault-Tolerant Computing (FTCS '96)
Analysis of the zeroconf protocol using UPPAAL
EMSOFT '06 Proceedings of the 6th ACM & IEEE International conference on Embedded software
Logical Specification and Analysis of Fault Tolerant Systems Through Partial Model Checking
Electronic Notes in Theoretical Computer Science (ENTCS)
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We present a systematic approach to design and verification of fault-tolerant components with real-time properties as found in embedded systems. A state machine model of the correct component is augmented with internal transitions that represent hypothesized faults. Also, constraints on the occurrence or timing of faults are included in this model. This model of a faulty component is then extended with fault detection and recovery mechanisms, again in the form of state machines. Desired properties of the component are model checked for each of the successive models. The models can be made relatively detailed such that they can serve directly as blueprints for engineering, and yet be amenable to exhaustive verification. The approach is illustrated with a design of a triple modular fault-tolerant system that is a real case we received from our collaborators in the aerospace field. We use UPPAAL to model and check this design. Model checking uses concrete parameters, so we extend the result with parametric analysis using abstractions of the automata in a rigorous verification.