A HyperTransport 3 Physical Layer Interface for FPGAs

Authors:
Heiner Litz;Holger Froening;Ulrich Bruening
Affiliations:
Computer Architecture Group, ZITI, University of Heidelberg, Mannheim, Germany 68131;Computer Architecture Group, ZITI, University of Heidelberg, Mannheim, Germany 68131;Computer Architecture Group, ZITI, University of Heidelberg, Mannheim, Germany 68131
Venue:
ARC '09 Proceedings of the 5th International Workshop on Reconfigurable Computing: Architectures, Tools and Applications
Year:
2009

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Abstract

This paper presents the very first implementation of a HyperTransport 3 physical layer interface for Field Programmable Gate Arrays. HyperTransport is a low latency, high bandwidth point-to-point interconnect technology that can be used to directly connect hardware accelerators to AMD's Opteron CPUs. Providing support for HyperTransport 3 on FPGAs is highly relevant for increasing the performance of accelerators based on reconfigurable logic. This paper shows the challenges of such an implementation and novel ideas to solve them successfully. A new architecture is presented that uses Fast Serializer Logic to keep up with the increasing speeds of current host interface protocols. A solid evaluation is provided using a specially developed FPGA board as a verification platform.