The AMD Opteron Northbridge Architecture

  • Authors:
  • Pat Conway;Bill Hughes

  • Affiliations:
  • Advanced Micro Devices;Advanced Micro Devices

  • Venue:
  • IEEE Micro
  • Year:
  • 2007

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Abstract

To increase performance while operating within a fixed power budget, the AMD Opteron processor integrates multiple x86-64 cores with a router and memory controller. AMD's experience with building a wide variety of system topologies using Opteron's HyperTransport-based processor interface has provided useful lessons that expose the challenges to be addressed when designing future system interconnect, memory hierarchy, and I/O to scale with both the number of cores and sockets in future x86-64 CMP architectures.