Tile-Based Fault Tolerant Approach Using Partial Reconfiguration

Authors:
Atsuhiro Kanamaru;Hiroyuki Kawai;Yoshiki Yamaguchi;Morisothi Yasunaga
Affiliations:
Graduate School of Systems and Information Engineering, University of Tsukuba, Tsukuba, Japan 305-8573;Graduate School of Systems and Information Engineering, University of Tsukuba, Tsukuba, Japan 305-8573;Graduate School of Systems and Information Engineering, University of Tsukuba, Tsukuba, Japan 305-8573;Graduate School of Systems and Information Engineering, University of Tsukuba, Tsukuba, Japan 305-8573
Venue:
ARC '09 Proceedings of the 5th International Workshop on Reconfigurable Computing: Architectures, Tools and Applications
Year:
2009

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Abstract

This paper deals with a dependable computing system using a reconfigurable device. The work carried out for this purpose of this study involved the proposition of a fault-tolerant approach which covers microprocessors. TFT, which is short for tile-based fault tolerant approach, has the intermediate layer which makes the connection between physical circuit layout and logical circuit layout for use in partial and dynamic reconfiguration. The reconfiguration is effectively utilized for online replacement of failed circuits. An advantage of TFT is that there is no conflict with other fault-tolerant approaches, and therefore TFT is freely available in the construction of dependable systems.