Incremental Cryptography: The Case of Hashing and Signing
CRYPTO '94 Proceedings of the 14th Annual International Cryptology Conference on Advances in Cryptology
OCB: A block-cipher mode of operation for efficient authenticated encryption
ACM Transactions on Information and System Security (TISSEC)
Multi-gigabit GCM-AES Architecture Optimized for FPGAs
CHES '07 Proceedings of the 9th international workshop on Cryptographic Hardware and Embedded Systems
I2CSec: A secure serial Chip-to-Chip communication protocol
Journal of Systems Architecture: the EUROMICRO Journal
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This paper presents an AES-GCM) core. This core has been designed and implemented taking into account two main aspects: It should provide a real throughput, capable of feeding a Gigabit Ethernet, and should be implemented in a commercial FPGA as part of a System-on-a-Chip (SoC). The AES-GCM encryption/authentication algorithm is of key importance as the fact of being introduced in four different standards, from Ethernet to mass storage devices, suggests. This algorithm is interesting because of two different reasons, first it provides authentication and encryption at the same time, and second its structure is highly parallelized. It is composed of two main blocks: an encryption core (AES in current standards) and a Galois Field multiplier.