Moebius circuit: dual-rail dynamic logic for logic gate level pipeline with error gate search feature

Authors:
MyeongGyu Jeong;Toru Nakura;Makoto Ikeda;Kunihiro Asada
Affiliations:
The University of Tokyo, Tokyo, Japan;The University of Tokyo, Tokyo, Japan;The University of Tokyo, Tokyo, Japan;The University of Tokyo, Tokyo, Japan
Venue:
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Year:
2009

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Abstract

We have introduced the concept of the Moebius strip into LSI circuit design, realizing 8.4 FO4-Inverter throughput for any kind of digital logic circuit. The Moebius circuit operates in a logic gate level pipeline, and has error detection and error gate search features, using a self-timed architecture.