A ubiquitous processor embedded with progressive cipher pipelines

Authors:
Masa-aki Fukase;Atsuko Yokoyama;Tomoaki Sato
Affiliations:
Hirosaki University, Hirosaki, Japan;Hirosaki University, Hirosaki, Japan;Hirosaki University, Hirosaki, Japan
Venue:
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Year:
2009

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Abstract

A ubiquitous processor developed for multimedia mobile use follows the parallelism of multicore and multiple pipelines. Cipher pipelines are dedicated for hardware cryptography that implements the progressive scheme of random number addressing achieved by directly connecting a built-in RNG (random number generator) to the address line of data cache. This makes transfer between register file and data cache microarchitectural transposition. The SIMD execution by the cipher pipeline has practical ability for ad-hoc network to keep the temporary security of multimedia data without permanent network infrastructure.