Experimental threshold voltage fluctuations of 30nm-NMOS-transistors manufactured by a lithography independent structure definition process

  • Authors:

  • John T. Horstmann;Klaus T. Kallis;Horst L. Fiedler

  • Affiliations:

  • Faculty of Electrical Engineering and Information Technology, Chair Electronic Devices of Micro and Nano Technique, Chemnitz University of Technology, Reichenhainer Strasse, 70, 09107 Chemnitz, Ge ...;Faculty of Electrical Engineering and Information Technology, Intelligent Microsystems Institute, Technical University of Dortmund, Emil-Figge-Street, 68, 44221 Dortmund, Germany;Faculty of Electrical Engineering and Information Technology, Intelligent Microsystems Institute, Technical University of Dortmund, Emil-Figge-Street, 68, 44221 Dortmund, Germany

  • Venue:
  • Microelectronic Engineering
  • Year:
  • 2009

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Abstract

NMOS-transistors with a minimum gate length of 30nm are fabricated with a lithography independent structure definition process for the gate definition. This way these very small transistors are patterned only by applying conventional optical lithography. The technique leads to an excellent homogeneity and uniformity of the channel length which enables a trustworthy statistical analysis of the electrical transistor parameters, especially of the threshold voltage. The fluctuations of the threshold voltage increase very dramatically with decreasing device dimensions and could become a major road blocker for the further device scaling. The experimental results are compared to a simple law of area by Lakshmikumar [K.R. Lakshmikumar, R.A. Hadaway, M.A. Copeland, IEEE Journal of Solid-State Circuits, 12(6) (1986) 1057-1066] showing a difference of approximately factor 2 and to newer atomistic simulations showing a good agreement. From these results strategies to compensate that strong increase of physically caused parameter fluctuations are derived.