Low-Voltage Low-Power Highly Linear Down-Sampling Mixer in 65nm Digital CMOS Technology

  • Authors:

  • Kurt Schweiger;Horst Zimmermann

  • Affiliations:

  • Institute of Electrical Measurement and Circuit Design, Vienna University of Technology, Gusshausstrasse 25/35, 1040 Vienna, Austria, kurt.schweiger@tuwien.ac.at;Institute of Electrical Measurement and Circuit Design, Vienna University of Technology, Gusshausstrasse 25/35, 1040 Vienna, Austria, horst.zimmermann@ieee.org

  • Venue:
  • DDECS '08 Proceedings of the 2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems
  • Year:
  • 2008

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Abstract

A highly linear down-conversion mixer in a 65nm digital CMOS technology is presented. The mixer was fabricated in a tripple-well process which allows to use the bulk of NMOS transistors as inputs. In contrary to other works not the gate but the bulk connector is used for the input signal. A high IIP3 of + 18dBm was achieved with a power consumption of only 0.67mW from a 1.2V supply voltage. The mixer has a measured 1dB compression point of +7dBm. The input signal bandwidth lies beyond 2GHz.