Analysis and Design of Analog Integrated Circuits
Analysis and Design of Analog Integrated Circuits
Low-Voltage Low-Power Highly Linear Down-Sampling Mixer in 65nm Digital CMOS Technology
DDECS '08 Proceedings of the 2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems
Low-voltage low-power double bulk mixer for direct conversion receiver in 65nm CMOS
DDECS '09 Proceedings of the 2009 12th International Symposium on Design and Diagnostics of Electronic Circuits&Systems
Hi-index | 0.00 |
In this paper, the `mixing' mechanism of CMOS bulk-driven (BD) mixer is analyzed in detail. Based on the theoretical analysis, a novel method to improve harmonic mixing rejection (HMR) which is important for wideband mixer is proposed. Three BD mixers of different structures are designed in TSMC 65 nm technology to verify this design methodology. Simulation proves that HMR performance is improved for different mixer structures by following the methodology. The broadband HMR is robust under process, temperature, bias and local oscillator amplitude variation without sacrificing other performances. These proposed mixers offer conversion gain above 4.6, 驴0.5 and 11.0 dB, respectively, covering frequency from 850 MHz to 6 GHz. The simulated IIP3 are 14.51, 16.82 and 4.96 dBm respectively. Power consumptions are 0.96, 1.2 and 0.33 mW respectively under 1 V power supply.