Computing and Minimizing Cache Vulnerability to Transient Errors

Authors:
Wei Zhang
Affiliations:
Southern Illinois University Carbondale
Venue:
IEEE Design & Test
Year:
2009

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ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special Section on Networks on Chip: Architecture, Tools, and Methodologies

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Abstract

Using a cache vulnerability factor to measure the susceptibility of cache memories to transient errors at the architecture level can help designers make appropriate cost and reliability trade-offs at early design cycles. Two early write-back strategies can also improve the reliability of write-back data caches without compromising performance.