Dynamic weighting Monte Carlo for constrained floorplan designs in mixed signal application
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Algorithms for VLSI Physcial Design Automation
Algorithms for VLSI Physcial Design Automation
Computer Methods for Circuit Analysis and Design
Computer Methods for Circuit Analysis and Design
Automatic Synthesis and Simulation of Continuous-Time [Sigma-Delta] Modulators
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Modeling Layout Effects for Sensitivity-Based Analog Circuit Optimization
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Geometric programming for circuit optimization
Proceedings of the 2005 international symposium on Physical design
Robust analog/RF circuit design with projection-based posynomial modeling
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Design automation for analog: the next generation of tool challenges
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
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The deep sub-micron (DSM) process nodes are increasingly marred by layout-dependent effects. The principal reason preventing layout synthesis during circuit design is the cost of edition, verification and extraction of the intermediate solutions repeatedly. This paper proposes a circuit and layout co-optimization scheme through a novel parasitic model-building scheme that exchanges information between the two flows. A placement-based parasitic estimation method to provide parasitic estimations to schematic optimization tools while retaining their efficiency. Extracted parasitics and simulated performance data are imparted into parasitic macro-devices and performance sensitivities. As proved by experimental results, the flexibility of the parasitic models bridges the efficiency and accuracy void between schematic and physical design optimization to ensure rapid DSM design closure.