Global parametric faults in analogue integrated circuits: two approaches to classification with the use of differential evolution

Authors:
P. Jantos;D. Grzechca;T. Golonek;J. Rutkowski
Affiliations:
Faculty of Automatic Control, Electronics and Computer Sciences, Silesian University of Technology, Gliwice, Poland;Faculty of Automatic Control, Electronics and Computer Sciences, Silesian University of Technology, Gliwice, Poland;Faculty of Automatic Control, Electronics and Computer Sciences, Silesian University of Technology, Gliwice, Poland;Faculty of Automatic Control, Electronics and Computer Sciences, Silesian University of Technology, Gliwice, Poland
Venue:
ECC'08 Proceedings of the 2nd conference on European computing conference
Year:
2008

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Abstract

Two approaches to global parametric faults in analogue integrated circuits (AIC) classification are presented in this paper. Global parametric faults (GPF) and integrated circuits time domain response features are defined. The aforementioned features are extracted and classified with the use of an evolutionary algorithm - Differential Evolution. The presented methods are compared with the use of two practical examples and results are discussed.