Information Processing Letters
International Journal of Parallel Programming
Design and Evaluation of the Rollback Chip: Special Purpose Hardware for Time Warp
IEEE Transactions on Computers
Efficient algorithms for distributed snapshots and global virtual time approximation
Journal of Parallel and Distributed Computing - Special issue on parallel and discrete event simulation
GTW: a time warp system for shared memory multiprocessors
WSC '94 Proceedings of the 26th conference on Winter simulation
Non-interfering GVT computation via asynchronous global reductions
WSC '93 Proceedings of the 25th conference on Winter simulation
ACM Transactions on Modeling and Computer Simulation (TOMACS) - Special issue on modeling and analysis of stochastic systems
Parallel and Distribution Simulation Systems
Parallel and Distribution Simulation Systems
Experience with a New Distributed Termination Detection Algorithm
Proceedings of the 2nd International Workshop on Distributed Algorithms
HPDC '97 Proceedings of the 6th IEEE International Symposium on High Performance Distributed Computing
SIMULATION OF PACKET COMMUNICATION ARCHITECTURE COMPUTER SYSTEMS
SIMULATION OF PACKET COMMUNICATION ARCHITECTURE COMPUTER SYSTEMS
Nonblocking Checkpointing for Optimistic Parallel Simulation: Description and an Implementation
IEEE Transactions on Parallel and Distributed Systems
Conservative synchronization of large-scale network simulations
Proceedings of the eighteenth workshop on Parallel and distributed simulation
Distributed Simulation: A Case Study in Design and Verification of Distributed Programs
IEEE Transactions on Software Engineering
PADS '12 Proceedings of the 2012 ACM/IEEE/SCS 26th Workshop on Principles of Advanced and Distributed Simulation
| Hi-index | 0.00 |
We present a design for a hardware supported global synchronization unit that would be implemented on–chip and directly accessible by all processors in a multi–core architecture. This global synchronization unit will provide all processors with access to global state information from all other processors in just a few clock ticks, and can be used to perform highly efficient and scalable time synchronization for parallel simulations. Further, our design takes into account the possibility of transient messages, and allows for non–uniform look ahead between processors in conservative synchronization methods. Simulating this hardware in a system simulator, we demonstrate its ability to decrease the runtime of a low–look ahead network simulation by a factor of two over a shared–memory barrier synchronization.