Low-power application-specific processor for FFT computations

  • Authors:

  • Teemu Pitkanen;Jarmo Takala

  • Affiliations:

  • Tampere University of Technology, Department of Computer Systems, P.O.Box 553, FIN-33101, Finland;Tampere University of Technology, Department of Computer Systems, P.O.Box 553, FIN-33101, Finland

  • Venue:
  • ICASSP '09 Proceedings of the 2009 IEEE International Conference on Acoustics, Speech and Signal Processing
  • Year:
  • 2009

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Abstract

In this paper, we describe a processor architecture tailored for radix-4 and mixed-radix FFT algorithms, which have lower arithmetic complexity than radix-2 algorithms. The processor is based on transport triggered architecture and several optimizations have been used to improve the energy-efficiency. The processor has been synthesized on a 130nm standard cell technology and analysis show that a programmable solution can possess energy-efficiency comparable to a fixed-function ASIC.