Virtualizing network-on-chip resources in chip-multiprocessors
Microprocessors & Microsystems
Network-on-Chip virtualization in Chip-Multiprocessor Systems
Journal of Systems Architecture: the EUROMICRO Journal
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Network on Chip (NoC) paradigm has made it possible to concurrently run multiple applications on IP-core based System on Chip. It is therefore necessary to predict the multi-processor systems-on-chip communication, which is a critical issue and needs to be addressed by the right mix of soft and hard real-time guarantees. To meet this requirement state of the art packet switched networks-on-chip (NoC) provide different levels of quality of service (QoS) such as best effort (BE) and guaranteed throughput (GT). This paper presents a novel scheme which compares and evaluates the performance of guaranteed throughput and best effort traffic in Network-on-Chip under different synthetic traffic generators and highlights its dependence in terms of latency on the type of traffic patterns and on the topology selection (mesh and torus) of Network on Chip. It also explores the effect of various routing function such as dimension order, planar adapter, romm and valiant on latency of GT and BE traffic for mesh topology.