Impact analysis of performance faults in modern microprocessors
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
On the Impact of Performance Faults in Modern Microprocessors
Journal of Electronic Testing: Theory and Applications
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We discuss the results of an extensive fault simulation study involving the control logic of a modern Alpha-like microprocessor. In this comparative study, faults are injected in both the RT- and the Gate-Level description of the design and are simulated under actual workload of the microprocessor, which is executing SPEC2000 benchmarks. The objective of this study is to analyze and contrast the impact of RT- and Gate-Level faults on the instruction execution flow of the microprocessor. The key observation is a pronounced consistency in the type and frequency of Instruction Level Errors (ILEs) arising due to RT- vs. Gate-Level faults. The motivation for this work stems from the need to understand the relative importance of low-level faults based on their instruction-level impact, in order to appropriately allocate error detection and/or correction resources. Hence, the consistency revealed through this study implies that such decisions can be made equally effective based on RT-Level fault simulation results, as with their far more computationally-expensive Gate-Level equivalents.