An efficient non-blocking multithreaded embedded system
ICA3PP'10 Proceedings of the 10th international conference on Algorithms and Architectures for Parallel Processing - Volume Part I
Affinity-aware DMA buffer management for reducing off-chip memory access
Proceedings of the 27th Annual ACM Symposium on Applied Computing
Hardware-software coherence protocol for the coexistence of caches and local memories
SC '12 Proceedings of the International Conference on High Performance Computing, Networking, Storage and Analysis
Energy and performance exploration of accelerator coherency port using Xilinx ZYNQ
Proceedings of the 10th FPGAworld Conference
Hi-index | 0.00 |
In embedded systems, multiple cores mean multiple caches and often multiple cache levels. Consequently, maintaining coherency between the cores' caches and the data generated or consumed by I/O devices is challenging, with different solutions trading off hardware versus software complexity. The optimal approach for I/O data coherence depends on application and system characteristics, and might require a combination of techniques.