An efficient non-blocking multithreaded embedded system

Authors:
Joseph M. Arul;Tsung-Yun Chen;Guan-Jie Hwang;Hua-Yuan Chung;Fu-Jiun Lin;You-Jen Lee
Affiliations:
Department of Computer Science and Information Engineering, Fu Jen Catholic University, Hsin Chuang, Taipei, Taiwan, R.O.C.;Department of Computer Science and Information Engineering, Fu Jen Catholic University, Hsin Chuang, Taipei, Taiwan, R.O.C.;Department of Computer Science and Information Engineering, Fu Jen Catholic University, Hsin Chuang, Taipei, Taiwan, R.O.C.;Department of Computer Science and Information Engineering, Fu Jen Catholic University, Hsin Chuang, Taipei, Taiwan, R.O.C.;Department of Computer Science and Information Engineering, Fu Jen Catholic University, Hsin Chuang, Taipei, Taiwan, R.O.C.;Department of Computer Science and Information Engineering, Fu Jen Catholic University, Hsin Chuang, Taipei, Taiwan, R.O.C.
Venue:
ICA3PP'10 Proceedings of the 10th international conference on Algorithms and Architectures for Parallel Processing - Volume Part I
Year:
2010

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Abstract

Most embedded systems are designed to perform one or fewer specific functions It is important that the hardware and the software must closely interact to achieve maximum efficiency in all of these realms and overcome the drawbacks found in each aspect This research focuses on designing a totally new Instruction Set Architecture (ISA) as well as hardware that can closely tie together with the new emerging trend such as multithreaded multicore embedded systems This new ISA can efficiently execute simple programs in a much efficient way as well as have a better cache performance with less cache misses due to the way the program is split into non-blocking multithreading paradigm This particular research is aimed to compare the performance of this new non-blocking multithreaded architecture with the ARM architecture that is commonly used in an embedded environment It has a speedup of 1.7 in general compared to the MIPS like ARM architecture.