Hierarchical cache/bus architecture for shared memory multiprocessors
ISCA '87 Proceedings of the 14th annual international symposium on Computer architecture
An evaluation of directory schemes for cache coherence
ISCA '88 Proceedings of the 15th Annual International Symposium on Computer architecture
The effect of sharing on the cache and bus performance of parallel programs
ASPLOS III Proceedings of the third international conference on Architectural support for programming languages and operating systems
Multiple vs. wide shared bus multiprocessors
ISCA '89 Proceedings of the 16th annual international symposium on Computer architecture
ACM SIGARCH Computer Architecture News
Computer
Comparative evaluation of latency reducing and tolerating techniques
ISCA '91 Proceedings of the 18th annual international symposium on Computer architecture
Modeling the performance of limited pointers directories for cache coherence
ISCA '91 Proceedings of the 18th annual international symposium on Computer architecture
Computer Architecture in the 1990s
Computer
The directory-based cache coherence protocol for the DASH multiprocessor
ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
Serial Multiport Memory Multiprocessors
PARLE '89 Proceedings of the Parallel Architectures and Languages Europe, Volume I: Parallel Architectures
The design of the M3S: a multiported shared-memory multiprocessor
Proceedings of the 1992 ACM/IEEE conference on Supercomputing
Performance of the vectorial processor VEC-SM2 using serial multiport memory
ICS '96 Proceedings of the 10th international conference on Supercomputing
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A set of ultra high throughput (more than one Gigabits per second) serial links used as processor-memory network can lead to the starting up of a shared-memory massively parallel multiprocessor. The bandwidth of the network is far beyond values found in present shared-memory multiprocessor networks. To feed this network the memory must be serially multiported. Such a multiprocessor can actually be build with current technologies.This paper analyzes the characteristics of such a novel architecture, presents the solutions that must be considered and the practical problems associated with close of experiments. These results show then the way to effectively build this multiprocessor, taking into account main topics such as data coherency, latency time and scalability.