Multiprocessors with a serial multiport memory and a pseudo crossbar of serial links used s a processor-memeory switch

Authors:
Daniel Litaize;Omar Hammami;Mustapha Lalam;Adelaziz Mzoughi;Pascl Sinrat
Affiliations:
Institut de Recherche en Informatique de Toulouse, Laboratoire L.S.I. Université Paul Sabatier, 118 route de Narbonne 31077 TOULOUSE CEDEX;Institut de Recherche en Informatique de Toulouse, Laboratoire L.S.I. Université Paul Sabatier, 118 route de Narbonne 31077 TOULOUSE CEDEX;Institut de Recherche en Informatique de Toulouse, Laboratoire L.S.I. Université Paul Sabatier, 118 route de Narbonne 31077 TOULOUSE CEDEX;Institut de Recherche en Informatique de Toulouse, Laboratoire L.S.I. Université Paul Sabatier, 118 route de Narbonne 31077 TOULOUSE CEDEX;Institut de Recherche en Informatique de Toulouse, Laboratoire L.S.I. Université Paul Sabatier, 118 route de Narbonne 31077 TOULOUSE CEDEX
Venue:
ACM SIGARCH Computer Architecture News
Year:
1989

Citing 0
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The design of the M3S: a multiported shared-memory multiprocessor

Proceedings of the 1992 ACM/IEEE conference on Supercomputing

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Abstract

This paper presents an inventive information exchange pro-cess between the main memory and cache equipped processors. It makes use of serial multiport memories and high throughput serial transmission supports. It is then possible to consider the realization of a multiprocessor with a common memory shared by several hundreds processors set with a performance level close to that of a crossbar network one's without having its disadvantages. This exchange process generates a family of possible architectures in which serial transfers of informations are parallelized, in the contrary of conventional architectures which serialize parallel transfers of informations.