Bus-invert coding for low-power I/O
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Overview of candidate device technologies for storage-class memory
IBM Journal of Research and Development
Energy- and endurance-aware design of phase change memory caches
Proceedings of the Conference on Design, Automation and Test in Europe
A frequent-value based PRAM memory architecture
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Bit mapping for balanced PCM cell programming
Proceedings of the 40th Annual International Symposium on Computer Architecture
Optimizing video application design for phase-change RAM-based main memory
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Due to its great scalability potential, phase change memory has become a topic of great current interest. However, high write energy consumption appears to be one of the biggest challenges to be tackled before phase change memory can be adopted as a mainstream memory technology. This paper presents architecture level technique to reduce phase change memory write energy consumption through data manipulations. Motivated by the fact that phase change memory read incurs much less energy than write and write of different value to a phase change memory cell incurs largely different energy, we present two memory write data manipulation techniques that can effectively reduce the overall memory write energy consumption. Their effectiveness has been demonstrated based on mathematical analysis and computer system simulation using phase change memory as the main memory in the computer memory hierarchy. Significant energy savings with up to more than 60% have been shown over a wide range of computer system benchmarks.