ASIC design of a novel high performance neuroprocessor architecture for multi layered perceptron networks

• Authors: Igor Dantas dos Santos Miranda;Ana Isabela Araújo Cunha
• Venue: Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes
• Year: 2009

This paper presents a new processor architecture for high performance computing of fixed-point feedforward multi layered perceptron neural networks. The number of layers, the number of neurons in each layer, the weight values and the activation function look-up table are configurable parameters so that this system can be used for several neural network models. Low latency and high throughput are achieved by means of a massive parallel hardware that separates required arithmetical operations among many multiply-accumulate units (MAC) and adopts a dual core structure to alternate on data sets processing. In order to access weight values from MACs, dual port RAM modules and a special memory organization have been used, allowing simultaneous reading from both cores and decreasing the connection wiring. This neuroprocessor has been designed for ASIC implementation using CMOS 90 nm technology and standard cell methodology. A performance comparison between the proposed architecture and some commercial neuroprocessors has been made.