Voltage controlled delay line with phase quadrature outputs for [0.9-4] GHz F-DLL dedicated to zero-IF multi-standard LO

Authors:
Cédric Majek;Yann Deval;Hervé Lapuyade;Jean-Baptiste Bégueret
Affiliations:
University of Bordeaux, Bordeaux, France;University of Bordeaux, Bordeaux, France;University of Bordeaux, Bordeaux, France;University of Bordeaux, Bordeaux, France
Venue:
Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes
Year:
2009

Citing 2
Cited 0

RF microelectronics

RF microelectronics
A performance comparison of PLLs for clock generation using ring oscillator VCO and LC oscillator in a digital CMOS process

Proceedings of the 2004 Asia and South Pacific Design Automation Conference

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Abstract

This paper presents the design and measurement results of a novel VCDL (Voltage Controlled Delay Line). Based on the multiphase ring oscillator technique, it offers two outputs in phase quadrature. These last ones allow the Factorial DLL (F-DLL) to be zero-IF compliant and so a good candidate for multi-standard LO. The proposed circuit has been fabricated using 130 nm CMOS SOI technology from STMicroelectronics. Measurements confirm the low quadrature phase error of the topology and its ability to synthesize the [0.9-4] GHz band, being suited for GSM up to WIMAX applications.